This invention relates to an ISL to TTL translator. It relates particularly to a compact integrated circuit arranged within a single isolation region that will translate from an ISL signal level to a TTL signal level without loading the ISL transistor.
Integrated Schottky logic (ISL) is a relatively new form of logic useful in large scale integrated circuits. ISL was first described in IEEE Journal of Solid State Circuits, Volume SC-14, No. 3, June 1979 in a paper authored by Jan Lohstroh, entitled, "ISL, a Fast and Dense Lower Power Logic, Made in a Standard Schottky Process". ISL provides a good compromise between low power Schottky TTL (LSTTL) and integrated injection logic (I.sup.2 L). It satisfies a demand for a circuit that consumes less power and takes up less chip area than LSTTL and requires a faster speed than I.sup.2 L.
An ISL gate in its simplest form comprises a current source, a normally operated collector down NPN transistor with a merged PNP clamp, and one or more output Schottky diodes. The PNP clamp, which may consist of the combination of a lateral PNP and a vertical PNP transistor sharing the collector and base regions of the NPN transistor, operates to prevent the NPN transistor from going too deeply into saturation, thereby reducing the saturation delay.
Although the IEEE article referred to above states that it is possible to combine ISL with other forms of logic, such as ECL, I.sup.2 L, and TTL on the same chip, it does not describe any way of translating between ISL and TTL. The obvious way to translate between an ISL gate and a TTL gate is to simply add two additional ISL gates between the input ISL gate and the TTL gate. However, the two additional ISL gates, each in its own isolation island, occupies too much space and undesirably introduces additional time delay.
Interface circuits are well known for forms of logic other than ISL. In Japanese Kokai No. 53-57723, an interface circuit uses a PNP level shift transistor coupled to the output of the NPN I.sup.2 L transistor. However, that circuit merely accomplishes level shifting, and being applicable to I.sup.2 L rather than ISL, does not provide other advantages that are uniquely associated with ISL. Furthermore there is no disclosure of merging the two transistors in a single isolation island or tub.
British Patent application GB 2.0l5.840A also discloses an I.sup.2 L to TTL translator which accomplishes level translation, but here again has only the advantages associated with I.sup.2 L rather than ISL. Also, there is no disclosure of merging transistors in a single isolation tub.
European Patent application 0009083 discloses a CML to TTL interface circuit, and German Patent application 3.024.273 discloses an ECL to TTL interface circuit. Neither of those references discloses merging transistors in a single isolation tub, and furthermore both references require two power supplies.